Clock design log #1 - analogue board

Finally, some real meat! Construction-ish posts. I'll be breaking things up in to two posts from here on. First will be a "design log" where I will talk about the immediate design task and run through its constituent parts, and also provide design files like schematics and what not. Second will be a "build log" where I will build what I just wrote about, and post photos and discuss any troubleshooting etc that I had to do to make it work.

The first board that I'll be building is what I am referring to as the "analogue board". I call it that because it has the most amount of "analogue" electronics on it.

So lets get stuck in to it.

Power supply

I'm designing my clock to work off 9V DC, and the power supply is pretty basic really - it's your bog standard linear regulator circuit, and is mostly a kludge of what ever reference design(s) I could find on-line plus a few suggestions that I've seen thrown around at times. It uses a 7809 linear voltage regulator, a smoothing capacitor for the input side, and a full bridge rectifier - because just like an amp that doesn't go to 11, anything less than a full bridge just isn't worth it.

The power source will be 12V AC from a wall adapter, and it is important to note that a power adapter that outputs AC is essential, as the AC is used to create the most fundamental timing signal within the clock since I'm not using any form of local oscillator.

AC_CLK/ generator

This is a circuit used to generate a clock signal which I call AC_CLK/. This is the most fundamental clock signal, as it is not only used to advance the time of the clock itself, but it is also used to reset various SR latches which generate other signals.

In a nutshell, instead of feeding the AC waveform directly in to my circuit, I first feed it through this circuit which uses three MOSFETs formed as a chain of inverters, and such that its output voltage is the system voltage of 9V DC. As the AC waveform goes high, the output is shunted down to ground. As the AC waveform goes low, the output signal goes high. This produces a roughly square wave output to the tune of the input AC signal.

Other circuits might use something like a schmitt trigger which will produce a "pure" square wave from a sine wave, and can also help to produce a clean square wave from an otherwise noisy signal. I don't expect the input AC waveform to be particularly noisy, so a schmitt trigger is not necessary and this simple circuit should work just fine for my needs. If you're interested in learning some more about how schmitt triggers work, check out this video and this video.

Power on reset delay

This is a "RC" (Resistor Capacitor) circuit. A pair of resistors create a voltage divider of which the high side resistor also limits the amount of current that the capacitor can draw to charge up. As the capacitor is charging it starves the gate of a MOSFET until such a time that it is sufficiently charged that the MOSFET is able to turn on. The MOSFET is actually acting as an inverter or NOT gate. When the MOSFET is off, current is allowed to flow from the output of the gate in to the reset mux, and a high input to the reset mux will assert a reset state within the clock. When the MOSFET eventually turns on, it shunts its output down to ground and the reset state is removed until power cycled.

I don't technically need this, as I could simply reset the clock manually once it is powered on, but I thought it was a nice little addition to ensure it powers up as "all zeros".

Reset mux

The reset mux is just an OR gate. It has two inputs, one of which comes from the power on reset delay circuit as described above, and the other from a button that the user can press to reset the clock at any time. Both signals combine through this circuit to produce a single "master clear" signal (called MCLR in my schematics) which is distributed throughout the clock. When asserted, this signal causes all counters and SR latches that produce the various clock signals to reset to default states (mostly all zeroes).

MCLR is also OR'ed with the output of the AC_CLK/ generator (a signal which starts its life as AC_CLK_GEN/) to produce the final AC_CLK/ signal. When MCLR is asserted by either the power on delay or reset button the AC_CLK/ signal is held high. Basically it ensures that all counters and latches within the clock will reset and be held stable.

Mains frequency prescaler

The mains frequency prescaler is implemented as a 6 bit ripple counter. It is combined with some additional gates which form a reset circuit. Without repeating myself too much (I covered a lot of the operating theory in design notes #5), when the prescaler reaches a certain value, an SR latch is set via an AND gate. When the SR latch is set, it resets the prescaler to zero, and the inverted output generates a new clock signal called 1PPS_CLK/.

I encourage you to read through the post I linked to above because it explains the operating theory in much more detail, including a timing diagram to demonstrate how all of the different signals are produced.

But the basic idea of the prescaler is to produce a clock pulse each second in order to advance the time module of the clock.

Schematics

And that about covers it for the circuits that are on the analogue board, so now lets look at the schematics for it. Full schematics are available within the GitHub repository as usual, and you'll need EAGLE to view them. I also provide them in PDF format if you don't have EAGLE. The schematics for this board are spread across two sheets/pages, one for the "analogue" side and the other for the "digital" side. The two files specific to this blog post are linked directly below.

I've included some notes within the schematics to try and explain briefly what each portion is for and what it does.

• GitHub repository
• analogue-board.sch EAGLE schematic file
• analogue-board.pdf

And with that, the first design log post is about done I think. The next post will cover the construction of the analogue board, and some details of testing/verification.

Clock design notes #5 - theory of operation

With all of the basics now covered, I thought it might be interesting to talk about the operation of the clock, and hopefully leave you with a good insight in to how it will function internally in order to produce the ever familiar output.

Here's a block diagram of all of the major parts to get started with:

And throughout the rest of this post I will (try to) explain the relationship of all of the items so that you understand what makes the clock tick (pun intended). There's a lot of repetition, so once you understand one little bit of it, you'll probably understand almost all of it.

But first, some terminology needs covering.

Things enclosed in parentheses indicate output signal names, for example, (AC_CLK/) indicates that AC_CLK/ is the signal output from that piece of the circuit.

Blue lines indicate clock signals, and there are numerous clock signals generated within the various modules of my clock which are used to advance successive counters, from seconds to minutes to hours to days and so on.

Green lines indicate counter outputs, and are usually multi-bit binary values. These outputs feed in to decoders that drive displays, and also in to reset circuitry that resets the counters and generates the various clock signals.

Red lines indicate reset signals which are used to either reset the entire clock (as in the case of MCLR), or only small portions of it, such as a single counter.

Black lines are generic signals.

Otherwise all of the boxes are labelled to indicate their purpose, and the lines are all capped off with an arrow head at one end indicating the direction that the signal is used.

Mains frequency prescaler

A simple circuit is used to produce a clock pulse of sorts from one half of the AC sinewave. This clock pulse is referred to as the AC_CLK/ signal because it pulses at the same frequency as the AC supply. It feeds the mains frequency prescaler, which increments on each falling edge of the AC_CLK/ signal. The forward slash indicates that it is an inverted signal, because AC_CLK/ is high when the AC waveform is low and vice versa.

This prescaler is tied to a reset circuit. The reset circuit can be configured to reset the prescaler at any value up to 63 because it's a 6 bit counter, so the clock can be used anywhere around the world, but in my case it will be configured to reset at 50 count because of where I'm located.

Upon the prescaler reaching 50 count, the reset circuit sets an SR latch sending its Q output high and complementary output (Q/ or "not Q") low. Q feeds in to the reset input of all of the D type flip flops that are part of the prescaler counter resetting them to 0, and Q/ creates a clock pulse to the seconds counter which is referred to as 1PPS_CLK/ (1 pulse per second).

On the rising edge of the next AC_CLK/ pulse, the SR latch will be reset causing its Q output to go low and releasing the reset on the counter, and Q/ output goes high. In this state the counter is at 0 count, and the next falling edge of AC_CLK/ will cause the counter to increment by 1.

Since I lack the requisite skills to make a fancy video, or maybe even an animation describing this, I'll try to illustrate it by way of another timing diagram. So here goes:

The very top signal of the timing diagram is AC_CLK/, oscillating back and forth between high and low states. The two signals below indicate the state of the SR latch outputs that form part of the reset circuit for the prescaler. Q feeds the reset of the counter, and Q/ forms the 1PPS_CLK/ signal to the seconds counter. PS 1 through PS 32 indicate the state of the Q outputs of the individual stages that make up the counter. A NOR gate connected to the complementary (i.e. Q/) outputs of PS 2, 16 and 32 acts as an AND gate to create a brief pulse in to the SR latch which triggers the reset when the count reaches 50.

So at the very left hand side of the timing diagram you see that PS 1, 2, 4 and 8 are low (0), and PS 16 and 32 are high (1), equalling a value of 48. At the falling edge of the first clock pulse you see that PS 1 transitions to a high state, so now the counter is representing a value of 49 (1+16+32). Then at the falling edge of the second clock pulse, PS 1 transitions to a low state, and that causes PS 2 to transition to a high state such that the counter now represents a value of 50.

As I have tried to represent in the diagram, it doesn't stay in this state for very long (on the order of nanoseconds really). At the point that PS 2, 16 and 32 are high, the NOR gate connected to the complement of those outputs goes high at its output (all low inputs = high output), and this causes the SR latch to invert its state. The Q output of the SR latch causes the counter to reset to 0, so you see after a short blip of PS 2 being high, it along with PS 16 and 32 all transition to a low state, and the counter now has a value of 0 with PS 1-32 all being low. And when Q/ of the SR latch transitioned to a low state, the falling edge of that signal would have caused the seconds counter to increment.

At the rising edge of the third pulse of AC_CLK/ you see that the SR latch inverts state again as it gets reset, and then at the falling edge of the third pulse you see that PS 1 goes high and we are back to a value of 1 again. It will continue incrementing until it reaches 50 count again, at which point it resets, generates another 1PPS_CLK/ pulse, and the seconds counter increments again. Lather, rinse, repeat until the end of time (or the power goes out).

Hopefully that gives you an idea of how the different clock pulses will be generated - they all operate in pretty much exactly the same way. Now I'll try and explain in a little more detail how everything ties together.

Seconds, minutes and hours

The seconds counter takes its input from the output of the prescaler, that is, the 1PPS_CLK/ signal. The seconds counter increments on the falling edge of the 1PPS_CLK/ signal which occurs when the prescaler reaches 50 count and resets. The seconds counter will count from 0 to 60, and upon reaching 60 count will reset itself to 0, so the effective count is 0-59.

Like the prescaler, the reset that occurs at 60 count sets an SR latch. The Q output of that SR latch goes high in order to reset the seconds counter to 0, and the Q/ output goes low generating the 1PPM_CLK/ (1 pulse per minute) clock signal which feeds the minutes counter.

At the next rising edge of AC_CLK/, the SR latch is reset and thus releases the reset on the seconds counter allowing it to start counting again at the next falling edge of 1PPS_CLK/.

Actually it's even a little more complicated than that, if you remember back to an earlier post I explained that each "counter" is really made up of two counters, each of which drives a display decoder. A "units counter" counts 0-9 and resets at 10, and that reset clocks the "tens counter" which counts 0-5 and resets at 6. That final reset at 6, which represents a total effective count of 0-59 is what generates the clock pulse to the next "counter".

The minutes counter will count 0-60 too, triggered by the falling edge of the 1PPM_CLK/ signal, and upon reaching 60, an SR latch is set, with the Q output resetting the counter to 0 and the Q/ output producing the 1PPH_CLK/ (1 pulse per hour) signal which feeds the hours counter.

I'm sure you can see where this is going ...

The hours counter counts 0-24 before resetting giving an effective count of 0-23, incrementing on the falling edge of the 1PPH_CLK/ signal, and resetting in the same maner as above with an SR latch generating a 1PPD_CLK/ (1 pulse per day) signal.

Pretty simple right?

Days and months

Days and months are a little more complicated. So lets start with a low hanging piece of fruit: day of the week.

Day of the week is a simple counter which is used to track the day of the week from Monday to Sunday, incrementing every falling edge of the 1PPD_CLK/ signal. It uses the same reset mechanism as all of the counters above, and upon reaching 7 it resets to 0 (with Monday being day 0 and Sunday being day 6). No clock signals are generated from its SR latch though, so I'll pretty much leave it there.

Day of the month is also incremented every falling edge of the 1PPD_CLK/ signal. But it includes a preset input to ensure that it always starts at a value of 1 since there is no day 0 in a month.

The reset circuit for day of month is also more complicated as it needs to handle a variety of situations, like resetting after the 30th or 31st day of certain months, or after day 28 or 29 in the month of February depending on whether it is a leap year or not. So it takes input from not only the day of month counter, but also the month counter, and the leap year toggle. The reset condition is generated based on the combinations of inputs from all of those sources according to this truth table:

If that looks slightly confusing (like, there aren't 32 days in any months you know of...), it's because that is the value that the day of month counter needs to be at in order to set the SR latch which causes the reset to occur, so the effective day count is one less than that since it will only stick around at 32 count for a few tens of nanaoseconds.

But the same basic principal applies in that it counts, and upon the above conditions being met it is reset, and an SR latch generates the 1PPMO_CLK/ (1 pulse per month) signal which causes the month counter to increment.

The month counter increments on the falling edge of the 1PPMO_CLK/ signal, and will reset at a count of 12 using the same SR latch mechanism. The same output of this latch which resets the month counter also feeds in to the leap year toggle to reset it at the end of the year such that the next year wont be counted as though it is a leap year - so you can set it at the start of the year, and not need to worry about turning it off. It's all about the little things in life...

I hope this has given you a good insight in to how the clock will function internally and how all of the various clock signals are generated and used.