Clock design log #1 - analogue board

Finally, some real meat! Construction-ish posts. I'll be breaking things up in to two posts from here on. First will be a "design log" where I will talk about the immediate design task and run through its constituent parts, and also provide design files like schematics and what not. Second will be a "build log" where I will build what I just wrote about, and post photos and discuss any troubleshooting etc that I had to do to make it work.

The first board that I'll be building is what I am referring to as the "analogue board". I call it that because it has the most amount of "analogue" electronics on it.

So lets get stuck in to it.

Power supply

I'm designing my clock to work off 9V DC, and the power supply is pretty basic really - it's your bog standard linear regulator circuit, and is mostly a kludge of what ever reference design(s) I could find on-line plus a few suggestions that I've seen thrown around at times. It uses a 7809 linear voltage regulator, a smoothing capacitor for the input side, and a full bridge rectifier - because just like an amp that doesn't go to 11, anything less than a full bridge just isn't worth it.

The power source will be 12V AC from a wall adapter, and it is important to note that a power adapter that outputs AC is essential, as the AC is used to create the most fundamental timing signal within the clock since I'm not using any form of local oscillator.

AC_CLK/ generator

This is a circuit used to generate a clock signal which I call AC_CLK/. This is the most fundamental clock signal, as it is not only used to advance the time of the clock itself, but it is also used to reset various SR latches which generate other signals.

In a nutshell, instead of feeding the AC waveform directly in to my circuit, I first feed it through this circuit which uses three MOSFETs formed as a chain of inverters, and such that its output voltage is the system voltage of 9V DC. As the AC waveform goes high, the output is shunted down to ground. As the AC waveform goes low, the output signal goes high. This produces a roughly square wave output to the tune of the input AC signal.

Other circuits might use something like a schmitt trigger which will produce a "pure" square wave from a sine wave, and can also help to produce a clean square wave from an otherwise noisy signal. I don't expect the input AC waveform to be particularly noisy, so a schmitt trigger is not necessary and this simple circuit should work just fine for my needs. If you're interested in learning some more about how schmitt triggers work, check out this video and this video.

Power on reset delay

This is a "RC" (Resistor Capacitor) circuit. A pair of resistors create a voltage divider of which the high side resistor also limits the amount of current that the capacitor can draw to charge up. As the capacitor is charging it starves the gate of a MOSFET until such a time that it is sufficiently charged that the MOSFET is able to turn on. The MOSFET is actually acting as an inverter or NOT gate. When the MOSFET is off, current is allowed to flow from the output of the gate in to the reset mux, and a high input to the reset mux will assert a reset state within the clock. When the MOSFET eventually turns on, it shunts its output down to ground and the reset state is removed until power cycled.

I don't technically need this, as I could simply reset the clock manually once it is powered on, but I thought it was a nice little addition to ensure it powers up as "all zeros".

Reset mux

The reset mux is just an OR gate. It has two inputs, one of which comes from the power on reset delay circuit as described above, and the other from a button that the user can press to reset the clock at any time. Both signals combine through this circuit to produce a single "master clear" signal (called MCLR in my schematics) which is distributed throughout the clock. When asserted, this signal causes all counters and SR latches that produce the various clock signals to reset to default states (mostly all zeroes).

MCLR is also OR'ed with the output of the AC_CLK/ generator (a signal which starts its life as AC_CLK_GEN/) to produce the final AC_CLK/ signal. When MCLR is asserted by either the power on delay or reset button the AC_CLK/ signal is held high. Basically it ensures that all counters and latches within the clock will reset and be held stable.

Mains frequency prescaler

The mains frequency prescaler is implemented as a 6 bit ripple counter. It is combined with some additional gates which form a reset circuit. Without repeating myself too much (I covered a lot of the operating theory in design notes #5), when the prescaler reaches a certain value, an SR latch is set via an AND gate. When the SR latch is set, it resets the prescaler to zero, and the inverted output generates a new clock signal called 1PPS_CLK/.

I encourage you to read through the post I linked to above because it explains the operating theory in much more detail, including a timing diagram to demonstrate how all of the different signals are produced.

But the basic idea of the prescaler is to produce a clock pulse each second in order to advance the time module of the clock.

Schematics

And that about covers it for the circuits that are on the analogue board, so now lets look at the schematics for it. Full schematics are available within the GitHub repository as usual, and you'll need EAGLE to view them. I also provide them in PDF format if you don't have EAGLE. The schematics for this board are spread across two sheets/pages, one for the "analogue" side and the other for the "digital" side. The two files specific to this blog post are linked directly below.

I've included some notes within the schematics to try and explain briefly what each portion is for and what it does.

• GitHub repository
• analogue-board.sch EAGLE schematic file
• analogue-board.pdf

And with that, the first design log post is about done I think. The next post will cover the construction of the analogue board, and some details of testing/verification.