Clock design log #2 - time module

The next board in the stack will be what I call the "time module". I call it this because it uses the 1PPS_CLK/ signal from the analogue board as its input, and using that it keeps track of the time time - and thats all it does. At what would be 24:00:00 it resets to 00:00:00 and generates the 1PPD_CLK/ signal which is used by what will probably be known as the "calendar module".

If you haven't already read my post about operating theory, it would be worth it before going much further with this post, it should help you understand whats going on in the schematics better. I'll re-cover a little bit of the theory here, but not in too much detail.

The basic premise of the time module is to implement 6 ripple counters, each of which has its own reset circuit that resets the counter at the appropriate value and clocks the next counter, and whos BCD values will be fed in to a set of decoders, each of which will drive a particular display at the front of the clock.

If you recall back to an earlier post, I mentioned that I had really wanted to implement these as 3 larger counters, but the decoders to drive the displays were getting very complicated, so I had to settle for 6 smaller counters. The idea behind this is that each portion of the display (that is, seconds, minutes, and hours) contains a "units" counter and a "tens" counter. A units counter will count 0-9 while a tens counter will count 0-5 (or 0-2 for hours). As each counter resets it clocks the next counter, so when the seconds unit counter "rolls over" from 9-0 it will clock the tens counter which will increment by 1. When the seconds tens counter "rolls over" from 5-0 it clocks the units counter for minutes, and so on and so forth. I guess its similar to how odometers in older cars work in a way.

As you're looking through the schematics for the time module, you'll see a lot of repeated circuitry which are D type flip flops that make up the individual stages of the ripple counters, and you will also see some other regular circuitry to the left of the ripple counters which is the reset logic for that counter. Above each counter will be a NOR gate facing in the opposite direction to all of the others, and this acts as an "AND" gate which feeds in to an SR latch. When the inputs to the "AND" gate are at appropriate values (in this case, all low because it uses inverted logic being a NOR gate) its output goes high and inverts the SR latch. When the SR latch inverts it causes the ripple counter to reset to 0 and generates a clock pulse to the next counter. The AC_CLK/ signal then inverts the SR latch again a short while later, and the counter can then start counting from 0 again.

Other gates just ensure that, for example, when MCLR is asserted (e.g. by pressing the reset button), if the input to the first stage of each counter was high it will actually be able to reset, and some other multiplexing such that either the SR latch or the MCLR signal is able to reset the counter. You will also notice that the minutes and hours units counters also include an input which allows those counters to be incremented manually by pressing a button. This is so that a value can be loaded in to those counters in order to set the time (e.g. after power on or user reset).

The hours counters are really the only "tricky" exception. Seconds and minutes reset at a decade boundary, but hours counts to 24 before resetting. So while there are still two gates which feed in to SR latches to initiate the reset, you'll notice that one of them actually causes not only the tens counter to reset but also the units counter, and in order to do that it takes input from the units and tens counters - that's unlike any of the others, which only take their inputs from the counter they are resetting.

And with that, the only thing left to do is to link you to the schematics:

• GitHub repo
• time-module.sch EAGLE schematic file
• time-module.pdf

Enjoy!