Ripple counters are used extensively in my clock. I use them as a prescaler for the mains frequency, and also for the various counters in the time and calendar "modules".
A ripple counter is an asynchronous counter. An external clock signal is applied only to the input of the first stage. The output of the first stage feeds in to the clock input of the second stage, and the output of the second stage feeds the next stage, and so on and so forth for as many stages as required. So as the name suggests, any changes that happen to the output state of each stage within the counter are going to ripple from one stage to the next - something like a line of dominos falling over.
This is basically the opposite of a synchronous counter, whose outputs all change at the same time based on a clock signal which is applied to all stages simultaneously. This results in an instantaneous change to all outputs at the same time in line with the clock signal.
I chose to use ripple counters instead of some other kind of synchronous counter (like one built from master-slave JK flip flops) because they are easier to implement with fewer transistors, and my clock doesn't have such an operating frequency where a synchronous counter might actually be necessary. For example, a modern CPU in a computer has an operating frequency somewhere in the multiple gigahertz (GHz) range (1GHz is 1 billion hertz... or 1 billion cycles per second), whereas my clock is timed from the AC mains frequency, which will be 50 or 60 hertz (hz) depending on where it is operated. So a little bit of delay here and there is not really detrimental to its operation - theres a relative eternity for things to settle down and work itself out (20ms per cycle at 50hz vs 1ns at 1GHz, several orders of magnitude).
So what is a ripple counter? It can be (as in my case) a series of D type flip flops cascaded together, and a D type flip flop is basically a series of SR latches.
So .. what is an SR latch? It's a very simple latch with two inputs, S (set) and R (reset), and two outputs, Q and the complement of Q (often referred to as "not Q"). The two inputs can be used to switch between two states: Q high and not Q low, or Q low and not Q high. In order to bring Q high, you must place a high signal on the set input. To bring Q low, you place a high signal on the reset input (not Q is always the opposite). Importantly, and as a latch, it holds the last state you applied even after you remove your input signal. Setting both the set and reset inputs high at the same time is an invalid input state, and at that point both Q and not Q will be low. As you'll see below, the topology of the SR latch circuit is symmetrical, so you can arbitrarily assign set and reset to either of the two inputs, the only rule is that Q will be the diagonally opposite output to the set input, and not Q will be diagonally opposite to the reset input.
You'll see them represented like this in my schematics, made easily out of two 2-input NOR gates:
You wont always see the inputs and outputs labelled in my schematics, and you might not always see the two outputs of the latch being used, but you will see this kind of circuit topology very frequently. I use a forward slash to indicate an inverted signal (i.e. the complement).
The explanation above is a bit brief, so I present to you a video by Ben Eater who explains this in more detail, and provides some practical examples to show its behaviour. It's a good video, and he has plenty more covering a project to build a small computer of sorts on a series of breadboards. Well worth watching his videos if you are interested in digital electronics, I highly recommend you check his channel out - you will learn a lot.
Moving on, three SR latches make a D type flip flop. In my clock I use D type flip flops with up to three inputs: clock (always), reset (always), and preset. Flip flops tend to be "edge triggered", that is, they will change state on either the rising or falling edge of the input clock pulse - which one depends on its construction. You may also be able to configure a flip flop to invert its state each time the clock input is pulsed, but this is not always the default behaviour. In my case, since I am using NOR logic, my flip flops will trigger and invert on the falling edge (high to low) of the input clock signal.
Setting the reset pin high will cause it to reset to a default state, in my case, Q being low. It's worth noting that while the clock input triggers on the falling edge, the reset input triggers on the rising edge.
In between resetting a D type flip flop and the next clock pulse, you can also feed in a preset signal. If the preset signal is high, the flip flop will start with Q being high, and the next clock pulse will transition Q to low. If the preset is left low, or no preset input is provided, the flip flop starts with Q low and the next clock pulse will transition it to high. A "full featured" D type flip flop will look like this in my schematics:
But once again, the inputs and outputs wont always be labelled, I've included them here to show you where those inputs are located. And as you can see, it's nothing more than three SR latches crossconnected in a specific way.
I don't have a particularly good video in mind to provide a link to to give a better explanation of the D type flip flop other than Ben Eaters video above, but I do have a link to a web page with a simulator that you can play with. It's not an exact representation of what I have here, but its pretty darn close and the operation is exactly the same. The only thing you need to do is set the D input to what ever the "not Q" output is before clicking the clock button, and you will see that you get the required behaviour which is to invert state on every clock pulse (you can see in my schematic above, not Q is tied to one of the inputs of GATE4, and that in the web based simulator, the same input to GATE4 is just a toggle).
There's also a mountain of additional reading on flip flops on this Wikipedia page.
Getting to the point where this all relates to a ripple counter... With the above theory in mind, recall that I have configured my D type flip flops to invert state on each clock pulse, and that they do this on the falling edge of the clock pulse.
If we start with all ripple counters in a reset state, such that Q is low for all outputs, and then feed a clock pulse in to the first stage (referred to as the "least significant bit") of the ripple counter, its Q output inverts to high on the falling edge of the clock pulse. On the next clock pulse, Q inverts back to low at the falling edge of the clock pulse. That output is also connected to the clock input of the second stage, so on the first stage output transitioning from high to low, Q of the second stage then inverts from low to high. We have just counted from 0 to 1 to 2. Now, the next clock pulse to the first stage inverts its Q output to high, and with high Q outputs on our first two ripple counter stages we are at binary value of 3. A further clock pulse to the first stage inverts its output to low, and that high to low transition causes the second stage to invert its Q output to low, and with the second stage output tied to the third stage clock input, that high to low transition causes the third stage to invert from low to high. We've now counted 0, 1, 2, 3, 4 (in binary, with the least significant bit on the right: 000, 001, 010, 011, 100).
But words aren't always interesting, so here's what is known as a timing diagram to visualise all of what I wrote above, plus a few extra clock pulses so you can see how it continues on:
As you can see, after the 8th clock pulse transitions high to low, all 3 stages return to low Q output state. It's no coincidence, a 3 bit counter can count from 0-7 which is 8 different values.
Bear in mind that this is just for demonstration purposes. Recall that a ripple counter is an asynchronous counter, so the outputs do not all transition instantly at the falling edge of the clock, rather, the falling edge of the clock is only when the "chain reaction" will begin, starting with the first stage and "rippling" through the counter as each stages output transitions from high to low, but only as far as the first stage that transitions low to high (because further stages will only be clocked when the preceeding stage transitions from high to low). The above diagram would indeed be accurate for a synchronous counter. Just a limitation of trying to draw it up in a spreadsheet I guess. But we are talking on the order of nanoseconds here, so it might be reasonably fair to say they do change "pretty much all at the same time".
If that still isn't enough to satisfy your understanding, I also provide a logicly file where you can see it in action for yourself. Heres a screenshot if you want to reconstruct it in the online demo:
If you look through logicly's options and ensure that the "Limit Propagation to Frame Rate" option is checked, then you may actually be able to see the ripple effect in action.
As I mentioned at the start of the post, I'm using ripple counters throughout my clock. In fact there will be 7 in total. I also use a lone D type flip flop as a toggle for leap year handling.
And finally, if you were wondering about transistor counts as per my recent posts, a D type flip flop with no preset input takes 14 transistors to implement or 15 with a preset input, but there is also some additional reset logic to go along with these counters, so more detailed counts will be provided in future posts when I discuss their specific design and construction.
A ripple counter is an asynchronous counter. An external clock signal is applied only to the input of the first stage. The output of the first stage feeds in to the clock input of the second stage, and the output of the second stage feeds the next stage, and so on and so forth for as many stages as required. So as the name suggests, any changes that happen to the output state of each stage within the counter are going to ripple from one stage to the next - something like a line of dominos falling over.
This is basically the opposite of a synchronous counter, whose outputs all change at the same time based on a clock signal which is applied to all stages simultaneously. This results in an instantaneous change to all outputs at the same time in line with the clock signal.
I chose to use ripple counters instead of some other kind of synchronous counter (like one built from master-slave JK flip flops) because they are easier to implement with fewer transistors, and my clock doesn't have such an operating frequency where a synchronous counter might actually be necessary. For example, a modern CPU in a computer has an operating frequency somewhere in the multiple gigahertz (GHz) range (1GHz is 1 billion hertz... or 1 billion cycles per second), whereas my clock is timed from the AC mains frequency, which will be 50 or 60 hertz (hz) depending on where it is operated. So a little bit of delay here and there is not really detrimental to its operation - theres a relative eternity for things to settle down and work itself out (20ms per cycle at 50hz vs 1ns at 1GHz, several orders of magnitude).
So what is a ripple counter? It can be (as in my case) a series of D type flip flops cascaded together, and a D type flip flop is basically a series of SR latches.
So .. what is an SR latch? It's a very simple latch with two inputs, S (set) and R (reset), and two outputs, Q and the complement of Q (often referred to as "not Q"). The two inputs can be used to switch between two states: Q high and not Q low, or Q low and not Q high. In order to bring Q high, you must place a high signal on the set input. To bring Q low, you place a high signal on the reset input (not Q is always the opposite). Importantly, and as a latch, it holds the last state you applied even after you remove your input signal. Setting both the set and reset inputs high at the same time is an invalid input state, and at that point both Q and not Q will be low. As you'll see below, the topology of the SR latch circuit is symmetrical, so you can arbitrarily assign set and reset to either of the two inputs, the only rule is that Q will be the diagonally opposite output to the set input, and not Q will be diagonally opposite to the reset input.
You'll see them represented like this in my schematics, made easily out of two 2-input NOR gates:
You wont always see the inputs and outputs labelled in my schematics, and you might not always see the two outputs of the latch being used, but you will see this kind of circuit topology very frequently. I use a forward slash to indicate an inverted signal (i.e. the complement).
The explanation above is a bit brief, so I present to you a video by Ben Eater who explains this in more detail, and provides some practical examples to show its behaviour. It's a good video, and he has plenty more covering a project to build a small computer of sorts on a series of breadboards. Well worth watching his videos if you are interested in digital electronics, I highly recommend you check his channel out - you will learn a lot.
Moving on, three SR latches make a D type flip flop. In my clock I use D type flip flops with up to three inputs: clock (always), reset (always), and preset. Flip flops tend to be "edge triggered", that is, they will change state on either the rising or falling edge of the input clock pulse - which one depends on its construction. You may also be able to configure a flip flop to invert its state each time the clock input is pulsed, but this is not always the default behaviour. In my case, since I am using NOR logic, my flip flops will trigger and invert on the falling edge (high to low) of the input clock signal.
Setting the reset pin high will cause it to reset to a default state, in my case, Q being low. It's worth noting that while the clock input triggers on the falling edge, the reset input triggers on the rising edge.
In between resetting a D type flip flop and the next clock pulse, you can also feed in a preset signal. If the preset signal is high, the flip flop will start with Q being high, and the next clock pulse will transition Q to low. If the preset is left low, or no preset input is provided, the flip flop starts with Q low and the next clock pulse will transition it to high. A "full featured" D type flip flop will look like this in my schematics:
But once again, the inputs and outputs wont always be labelled, I've included them here to show you where those inputs are located. And as you can see, it's nothing more than three SR latches crossconnected in a specific way.
I don't have a particularly good video in mind to provide a link to to give a better explanation of the D type flip flop other than Ben Eaters video above, but I do have a link to a web page with a simulator that you can play with. It's not an exact representation of what I have here, but its pretty darn close and the operation is exactly the same. The only thing you need to do is set the D input to what ever the "not Q" output is before clicking the clock button, and you will see that you get the required behaviour which is to invert state on every clock pulse (you can see in my schematic above, not Q is tied to one of the inputs of GATE4, and that in the web based simulator, the same input to GATE4 is just a toggle).
There's also a mountain of additional reading on flip flops on this Wikipedia page.
Getting to the point where this all relates to a ripple counter... With the above theory in mind, recall that I have configured my D type flip flops to invert state on each clock pulse, and that they do this on the falling edge of the clock pulse.
If we start with all ripple counters in a reset state, such that Q is low for all outputs, and then feed a clock pulse in to the first stage (referred to as the "least significant bit") of the ripple counter, its Q output inverts to high on the falling edge of the clock pulse. On the next clock pulse, Q inverts back to low at the falling edge of the clock pulse. That output is also connected to the clock input of the second stage, so on the first stage output transitioning from high to low, Q of the second stage then inverts from low to high. We have just counted from 0 to 1 to 2. Now, the next clock pulse to the first stage inverts its Q output to high, and with high Q outputs on our first two ripple counter stages we are at binary value of 3. A further clock pulse to the first stage inverts its output to low, and that high to low transition causes the second stage to invert its Q output to low, and with the second stage output tied to the third stage clock input, that high to low transition causes the third stage to invert from low to high. We've now counted 0, 1, 2, 3, 4 (in binary, with the least significant bit on the right: 000, 001, 010, 011, 100).
But words aren't always interesting, so here's what is known as a timing diagram to visualise all of what I wrote above, plus a few extra clock pulses so you can see how it continues on:
As you can see, after the 8th clock pulse transitions high to low, all 3 stages return to low Q output state. It's no coincidence, a 3 bit counter can count from 0-7 which is 8 different values.
Bear in mind that this is just for demonstration purposes. Recall that a ripple counter is an asynchronous counter, so the outputs do not all transition instantly at the falling edge of the clock, rather, the falling edge of the clock is only when the "chain reaction" will begin, starting with the first stage and "rippling" through the counter as each stages output transitions from high to low, but only as far as the first stage that transitions low to high (because further stages will only be clocked when the preceeding stage transitions from high to low). The above diagram would indeed be accurate for a synchronous counter. Just a limitation of trying to draw it up in a spreadsheet I guess. But we are talking on the order of nanoseconds here, so it might be reasonably fair to say they do change "pretty much all at the same time".
If that still isn't enough to satisfy your understanding, I also provide a logicly file where you can see it in action for yourself. Heres a screenshot if you want to reconstruct it in the online demo:
If you look through logicly's options and ensure that the "Limit Propagation to Frame Rate" option is checked, then you may actually be able to see the ripple effect in action.
As I mentioned at the start of the post, I'm using ripple counters throughout my clock. In fact there will be 7 in total. I also use a lone D type flip flop as a toggle for leap year handling.
The day of month counter is the only counter in the clock which accepts a pre-set value. This is so that each time it is reset it can be set to start counting from 1 instead of 0 like all of the other counters.
And finally, if you were wondering about transistor counts as per my recent posts, a D type flip flop with no preset input takes 14 transistors to implement or 15 with a preset input, but there is also some additional reset logic to go along with these counters, so more detailed counts will be provided in future posts when I discuss their specific design and construction.
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