Saturday 4 March 2017

Discrete NOR logic clock - Introduction

A few weeks ago I was watching a video by a YouTuber called Fran Blanche about the Apollo Guidance Computer DSKY interface. She is looking to build a replica, and had an opportunity to inspect some of the real deal items in person to take measurements and notes. You can check out that video here.

My interest was piqued, and I started doing some reading about the AGC and found that it was built entirely using NOR logic. Apparently, at the time, NOR was the most reliable type of logic gate available. As a point of interest, schematics and other information for the AGC are also available on this website.

If you're not familiar with logic gates, there are several different types that perform different functions, and when combined together can make things as complicated as a CPU in a computer for example. See more about the different types of logic gates on this Wikipedia page. Scroll down the page and you'll find links to further pages describing each type of gate in more detail.

Also, NOR, along with NAND, happen to be what are known as a "universal gates", and basically what that means is that using nothing but NOR (or NAND) logic you can build any other kind of logic gate. There is a Wikipedia article which covers it all with examples, so I wont re-hash here.

But in a nutshell, NOR logic is an OR gate with inverted output (the N stands for NOT). With a standard OR gate, if at least one input is high then its output will also be high, otherwise it will be low. With a NOR gate, if one or more inputs are high the output will be low, otherwise high. Heres a truth table to demonstrate the different input and output combinations of a 2-input NOR gate:


A and B are the inputs, and Q is the output. Additional inputs can be added for more complex logic, but the basic truth remains that the output of the NOR gate is only high when all of the inputs are low.

Theory aside, why is this even a topic of discussion, and why did I make a blog about it? Well, after discovering the AGC was built using NOR logic, I thought to myself that it would be an interesting challenge to build something using NOR logic. And that it could be interesting to cover the process. And it has been said that if you really want to understand something, you should build it.

Now, I'm not going to build a computer to fly me to the moon, but I was already planning to build a clock (because clocks are useful) using CMOS (4000 series) logic, so I thought that this would be a perfect project to satisfy the newly acquired interest. And then I thought I might go one step further and build it entirely of discrete components, because that would be rather impressive looking. To put it another way, I will build it out of individual transistors rather than using pre-packaged 4000 or 7400 series logic chips.

And with that, here is a summary of the functionality that my clock will have:

  • hh:mm:ss time readout using 7 segment displays, and specifically 24 hour time which is my preferred time format
  • Calendar readout using a combination of 7 and 16 segment displays (e.g. FR 03 MAR)
  • Leap year mode, which will need to be manually set during a leap year because I wont be counting years in my clock (I dont think it will be particularly useful) which will allow the calendar to properly handle the month of February
  • Timing will be sourced from the mains grid (but not at mains grid voltage obviously) because mains grid frequency is relatively consistent at 50 or 60hz depending on where you are (some clocks you find around your house, e.g. in the oven or microwave, probably work the same way)

And that will be it. I think that represents the most useful information that a clock could display. As a "nice to have" and if I can fit it in without too much additional complexity, an ability to dim or blank the display during certain hours of the day would be a nice feature (e.g. to keep a room, like a bedroom, as dark as possible).

A lot of the design work was complete by the time I started writing this blog. But thats ok. Some of the parts I need are on back order and I might not get them for another month, and I am still sourcing some others, so that gives me some time to play catch up and document the design process and explain the operating theory.

3 comments:

  1. Very interesting post! It got me thinking about two things:
    1) Karnough-maps are good for minimizing the circuit for one segment at a time. But obviously you also want to optimize across segments. I was trying something similar myself, but couldn't come up with anything better than just kinda "staring" at it all at once... What else I could imagine is writing a program that does an exhaustive search. Isn't there some *systematic* way to do this?
    2) Karnough-maps are designed to find minimal sum-of-products (OR-ed together AND-terms). But what if want to use other kinds of gates, like eg the universal NOR or NAND (only)? Can we find a way to somehow adapt to these?
    ___
    meisl / aka TheRealMeisl on YT

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    Replies
    1. I was re-reading the Wikipedia article about k-maps earlier today and I noticed something which I must have missed last time:

      "The Karnaugh map reduces the need for extensive calculations by taking advantage of humans' pattern-recognition capability."

      So even if you could write some software, if it doesnt already exist, it seems they are intended to be processable by the human brain. :-)

      Also, interesting concept re matching, say, a checkerboard pattern. I had a bit of a play and I think I came up with a solution for that using a pair of XOR, pair of XNOR, pair of AND and an OR gate:

      https://docs.google.com/spreadsheets/d/12GEKC7hadtHyxGLaN5LIKIaRc8lJIQMaItI2XOjvW5A/edit#gid=0

      You can build up that circuit using the on-line logic.ly demo to try it out (really wish I could build something on-line and share it, must submit a feature request for that).

      How you would represent this through min or maxterms though ... thats a head scratcher. Or maybe its beside the point..?

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  2. I had brought up the checkerboard example over at YT as a worst case to express as sum-of-products, it's a sum of 8 products with 4 factors each.
    But there is a very small solution if you use XOR gates:
    A XOR B XOR C XOR D
    Note that in your spreadsheet you have done the inverted example, ie a 1 output where the nr of input 1s is even, not odd. Anyways, the minimal solution for this would be
    A XNOR B XNOR C XNOR D
    ...or you could use the above XOR expression and invert it once in the end.

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